1. Field of the Invention
The present invention relates to a method of recognizing a connection of a reconstructing pattern in a printed wiring board, and in particular to a method for recognizing a connection of a reconstructing pattern in a printed wiring board when a circuit modification process after a printed board wiring is performed by a physical cutting, a jumper, and the like.
When a circuit realized on a printed wiring board as pattern-designed by a design supporting device there for and the like is modified, a cutting of a pattern, an addition of a jumper, and a deletion or addition of electric parts are performed to make the printed wiring board correspond to a modified circuit.
Since the works for cutting the pattern and for determining an additional position of the jumper of such a printed wiring board take time and easily cause errors as the circuit becomes complicated and the pattern is highly densified, it is demanded to realize a method of recognizing a connection of a reconstructing pattern in a printed wiring board.
2. Description of the Related Art
FIGS. 27A-27C show examples of circuit information and pattern information used in a conventional method (1) of recognizing a connection of a reconstructing pattern.
FIG. 27A shows circuit information, first edition before modification, in which net Nos.1 and 2 are respectively allotted to groups of lands (A, B, C) and (D, E) as connecting elements.
A design supporting device (not shown) connects lands A, B, C of the net No.1 in the order of the land A, a line L1, a via V1, a line L2, the land B, a line L3, and the land C based on the circuit information, first edition, and performs a pattern design for connecting lands D and E of the net No.2 in the order of the land D, a line L4, a via V2, a line L5, and the land E to output the connections as pattern information, first edition.
The pattern information, first edition is composed of the land (via) information (A, B, C, D, E, V1, V2), the line information (L1-L5), and net information. The net information is composed of the lands, which are the same as the lands of the circuit information, first edition for each of the net Nos.1 and 2, as well as the vias and the lines for connecting the lands, for each of the net Nos.1 and 2.
FIG. 27B shows second circuit information and pattern information when a circuit modification that lands A and B are connected to a land X added instead of the land C in the net No.1. is performed to the circuit connection of FIG. 27A.
Namely, in the circuit information, second edition, the lands of net No.11 corresponding to the net No.1 of the circuit information, first edition is modified to the lands A, B and X, while the lands D and E of net No.12 corresponding to the net No.2 have no modification.
In the pattern information, second edition, the land X is added to the land information, the line information has no modification, the land C and the line L3 are deleted from the connecting elements of the net No.11 in the net information and the land X is added to the same, and the connecting elements of the net No.12 has no modification.
FIG. 27C shows an image of files of the information shown in FIGS. 27A and 27B. Pattern information, first edition file F1 is prepared from circuit information, first edition file F1, and circuit information, second edition file F2 is prepared according to a circuit modification, so that pattern information, second edition file F21 is prepared from the circuit information, second edition file F2.
The pattern information, first edition file F11 is compared with the pattern information, second edition file F21 so that a physically different part is found to perform a pattern reconstruction.
This method has to retain the pattern information corresponding to the circuit information for every circuit modification as a file so that the storage capacity required becomes large.
FIGS. 28A and 28B show examples of the circuit information and the pattern information used in a conventional method (2) of recognizing a connection of a reconstructing pattern. In these examples, the circuit information, first edition file F1, the pattern information, first edition file F11, and the circuit information, second edition file F2 are the same as those shown in FIGS. 27A-27C. However, in the pattern information after the circuit modification, the line L2 which mutually connects the lands B and C is assumed to be not connected to the land B, as shown in FIG. 28B.
Accordingly, although the pattern information, second edition file is not used as modified pattern information to require a smaller storage capacity, the propriety of dummy portions becomes less clear so that the required storage capacity increases as the frequency of the modification increases.
Furthermore, since it is premised in this method that the pattern information has no short circuit and a line element is required to be separated in a psudo form, the best section for separation can not be detected in a loop pattern or a large area pattern.
FIG. 29 shows a data structure example of a pattern link table (hereinafter abbreviated as PTLNK table) 10, a land table (hereinafter abbreviated as LAND table) 20, and a line table (hereinafter abbreviated as LINE table) 30 used by prior art methods (1) and (2) of recognizing a connection of a reconstructing pattern. In this example, the pattern information is composed of the PTLNK table 10, the LAND table 20, and the LINE table 30 in order to recognize the connection of connecting elements such as lands, lines, and the like.
Arrangement elements 11, 12, . . . etc. of the PTLNK table 10 corresponds to the net Nos.1, 2, . . . etc. shown in FIGS. 27A-27C, wherein the arrangement elements 11, 12, . . . etc. are composed of land link pointers (hereinafter abbreviated as LNDLNKP pointer) and line link pointers (hereinafter abbreviated as LINLNKP pointer) which respectively point the land to be connected in the LAND table 20 and the line in the LINE table 30.
The LAND table 20 and the LINE table 30 are respectively composed of the arrangement elements corresponding to the lands and lines which are the connecting elements of the whole circuit. The arrangement elements 21-27, . . . etc. of the LAND table 20 are composed of the lands (or vias) A-E, V1, V2, . . . etc. and the land link pointers which point the arrangement elements of the lands to be connected to the above-mentioned lands (or vias) A-E, V1, V2, . . . etc. These land link pointers will be also hereinafter abbreviated by the same reference character as the LNDLNKP pointer of the PTLNK table. The LINE arrangement elements 31-35, . . . etc. of the LINE table 30 are composed of the lines L1, . . . L5, etc. and the line link pointers which point the arrangement elements of the lines to be connected to the above-mentioned lines L1, . . . L5, . . . etc. These line link pointers will be also hereinafter abbreviated as LINLNKP pointer in the same manner.
For instance, the LNDLNKP pointer of the arrangement element 11 in the PTLNK table 10 points the arrangement element 21 of the LAND table 20 so that the LNDLNKP pointer of the arrangement element 21 points the arrangement element 22. Hereafter, the arrangement elements 23 and 26 are sequentially pointed in the same manner, so that when the LNDLNKP pointer of the arrangement element 26 is set to xe2x80x9c0xe2x80x9d, the link of the land by the pointer is ended.
In addition, the LINLNKP pointer of the arrangement element 11 in the PTLNK table 10 points the arrangement element 31 in the LINE table 30, the LINLNKP pointer of the arrangement element 31 points the arrangement element 32, and the LINLNKP pointer of the arrangement element 32 points the arrangement element 33, so that when the LINLNKP pointer of the arrangement element 33 is set to xe2x80x9c0xe2x80x9d, the link of the line by the pointer is ended.
Accordingly, all of the lands and lines which the PTLNK arrangement element 11 points are the lands A-C, the via V1, and the lines L1-L3.
Likewise, all of the lands and lines pointed by the LNDLNKP pointer and the LINLNKP pointer of the arrangement element 12 in the PTLNK table 10 are lands D, E, the via V2, and the lines L4, L5.
This means that the lands A-C, the via V1, and the lines L1-L3 have belonged to the net of No.1 corresponding to the PTLNK arrangement element 11 and that the lands D, E, the via V2, and the lines L4, L5 have belonged to the net of No.2 corresponding to the PTLNK arrangement element 11.
FIGS. 30A and 30B show an embodiment of a net and a prior art physical connection table (hereinafter occasionally referred to as PLINK table) 50 for recognizing the physical connection of the net.
FIG. 30A specifically shows an arrangement of the lands A-D, the via V1, and the lines L1-L6 which are the connecting elements of the net No.1 on a pattern wiring board. In FIG. 30A, the land A, the via V1, the lands B, C, and the lines L1, L2, L4 are sequentially connected, so that the land D is further connected to the land B with the line L3 and is connected to the land C with the lines L6 and L5.
FIG. 30B specifically shows the PLINK table 50 having a forward direction connecting direction address (hereinafter referred to as KP address) for recognizing the physical connection of the net of FIG. 30A.
Namely, the lands A-D, the via V1, and the lines L1-L6 which are the connecting elements are respectively set corresponding to the arrangement addresses xe2x80x9c1-11xe2x80x9d, so that KP addresses are respectively set corresponding to the connecting elements.
If the land A for instance is made a reference (a starting point), the KP address of the land A is set to xe2x80x9cxe2x88x921xe2x80x9d, the KP address of the line L1 connected to the land A is set to xe2x80x9c1xe2x80x9d which is the arrangement address of the land A, and the KP address of the via V1 connected to the line L1 is set to xe2x80x9c6xe2x80x9d which is the arrangement address of the line L1.
Hereafter, the KP addresses of the line L2, the land B, the line L4, the land C, and the line L5 are respectively set to xe2x80x9c5xe2x80x9d, xe2x80x9c7xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c9xe2x80x9d, and xe2x80x9c3xe2x80x9d, as well as the KP addresses of the line L3, the land D, and the line L6 are respectively set to xe2x80x9c2xe2x80x9d, xe2x80x9c8xe2x80x9d, and xe2x80x9c4xe2x80x9d in the same manner.
Accordingly, by repeating the search or retrieval of the line L1 having the KP address of the same value as the arrangement address xe2x80x9c1xe2x80x9d from the reference land A and the search of the via V1 having the same KP address as the arrangement address xe2x80x9c6xe2x80x9d of the line L1, it becomes possible to sequentially search and recognize the connecting elements physically connected to the land A.
In such a prior art method of recognizing a connection of a reconstructing pattern in a printed wiring board, it can be recognized that e.g. in FIG. 30A the line L5 is connected to the land C since the KP address of the line L5 is xe2x80x9c3xe2x80x9d and that the line L6 is connected to the land D since the KP address of the line L6 is xe2x80x9c4xe2x80x9d.
However, it can not be recognized that the lines L5 and L6 are connected. This is because the land B, the line L4, the land C, the lines L5 and L6, the land D, and the line L3 form a loop pattern.
When the circuit modification for separating e.g. the land D from the lands A, B, and C is performed, it is found in the PLINK table 50 that the line L3 of the arrangement address xe2x80x9c8xe2x80x9d can be cut from the KP address xe2x80x9c8xe2x80x9d of the land D. However, the connection between the land D, the lines L6 and L5, and the land C is not yet recognized.
In order to recognize this connection, it has been required to prepare the PLINK table 50 in which the connection order is change to recognize the connection of the lines L5 and L6.
In the presence of many loop patterns and many connecting elements of this kind, there has been a problem that it takes time to set again or reset the KP addresses by referring to the coordinate.
Also, since a large area pattern has been treated as diagram information so that the cutting of the large area pattern is performed by a diagram operation in the prior art method, there has been a problem that the process speed is delayed as diagram data increase.
It is accordingly an object of the present invention to provide a method of recognizing a connection of a reconstructing pattern in a printed wiring board performing a circuit modification process after a printed board wiring wherein a required storage capacity is small and the physical connection of connecting elements including a loop pattern and a large area pattern is recognized at a high speed to perform the circuit modification process.
In order to achieve the above-mentioned object, a method of recognizing a connection of a reconstructing pattern in a printed wiring board, according to claim 1, of the present invention comprises the step of; preparing a physical connection table (PLINK table), corresponding to each net, which has a connecting direction address (KP address) indicating a (forward) connection order of connecting elements with a predetermined connecting element being made a starting point and a backward connecting direction address (NKP address) set based on the connecting direction address and indicating a backward connection order to the (forward) connection order and which enables a physical connection of the connecting elements to be recognized, based on a pattern input information table indicating a physical state of the connecting elements.
Namely, the KP addresses indicating the connection order of the connecting elements are set in the PLINK table, with a predetermined connecting element being made a reference element as a starting point, based on the physical state of the connecting elements which the pattern input information table indicates. Furthermore, the NKP addresses indicating the backward connection order to the (forward) connection order of the KP addresses can be set in the PLINK table based on the KP addresses.
As a result, it becomes possible to recognize the physical connecting state of the connecting elements of the net based on the KP addresses and the NKP addresses as set with a less storage capacity and at a high speed.
Also, in the present invention according to claim 2, the connecting direction address and the backward connecting direction address of the physical connection table may be modified to a connecting direction address and a backward connecting direction address corresponding to a modified circuit to recognize the physical connection.
Namely, the physical connection of the connecting elements after the circuit modification can be recognized by preparing the PLINK table in which the KP addresses and the NKP addresses after the modification are set based on the KP addresses and the NKP addresses before the circuit modification.
As a result, it becomes possible to recognize the physical connection of the connecting elements at a high speed and to perform the circuit modification process.
Also, in the present invention according to claim 3, the connecting elements may be composed of a land and a line, and the land may include a via, a manual land, and an external land for parts which are not mounted on the printed wiring board, and the line may include a jumper for mutually connecting the connecting elements on the printed wiring boards, the external land and the connecting elements, and the external lands.
Namely, in addition to the part land, the via, the manual land, and the external land which is not on the wiring board are treated as a land. Also, besides an ordinary line, the jumper connecting the connecting elements on the wiring board, the external lands, as well as the connecting element and the external land are treated as a line. The land and the line can be treated in the unified form as a connecting element.
As a result, it becomes possible to recognize the physical connection between the part land, the via, the manual land, the external land, the line, and the jumper which are all connecting elements at a high speed.
Also, in the present invention according to claim 4, the predetermined connecting element may comprise a land, and the connecting direction address may be set with only a connection order from the starting land set in the physical connection table to a second land being reversed and the second land being made a starting point.
Namely, the KP addresses with the second land being made a reference land are set again or reset with only the connection order from the starting land to the second land being reversed and with the other KP addresses being not modified.
As a result, it becomes possible to obtain (repaint) the KP addresses whose reference land is modified at a high speed.
Also, in the present invention according to claim 5, whether or not a line whose backward connecting direction address indicating that the line is not connected is physically connected to a second connecting element may be determined based on the pattern input information table, and when the line is connected it may be recognized that the net includes a loop pattern.
Namely, the (forward) connecting direction address and the backward connecting direction address indicate only the connection order, so that all of the connecting states of the connecting elements in the net are not indicated. Thus, whether or not the line recognized as being not connected to the other connecting elements is connected in the actual net is determined based on the pattern input information table, so that when the line is connected it is recognized that the net includes the loop pattern.
Accordingly, it becomes possible to determine whether or not the net includes the loop pattern by confirming the connection of only lines recognized as being not connected to the connecting elements. As a result, it becomes possible to recognize the loop pattern at a high speed.
Also, in the present invention according to claim 6, a cutting of the line may be recognized by being regarded as a temporarily cut line, and the jumper may be recognized by being regarded as a line between the elements.
Namely, it is possible to confirm that the circuit modification is accurately performed by regarding the line as being temporarily cut and by regarding the added jumper as a line when the circuit modification is performed. As a result, it becomes possible to perform the circuit modification process at a high speed.
Also, in the present invention according to claim 7, a physical connection table where two nets are connected with the jumper to form a single net may be prepared by combining a physical connection table of two nets and a physical connection table of the jumper, and the connecting direction address and the backward connecting direction address of the combined physical connection table may be set based on the connecting direction address and the backward connecting direction address of original physical connection tables.
Namely, the physical connection table where the physical connection table of two nets and the physical connection table of only the jumper connecting the two nets are combined is prepared so that the combined table is made a physical connection table of a net where the two nets are connected with the jumper.
Then, the connecting direction address and the backward connecting direction address of the physical connection table of the nets connected based on the connecting direction address and the backward connecting direction address of the original connecting table can be set.
As a result, it becomes possible to set the physical connection table of the combined nets at a high speed and to recognize the physical connecting state of the combined connecting elements.
Also, in the present invention according to claim 8, the connecting elements may further include a large area pattern, and the large area pattern may be regarded as being composed of one of a peripheral line of the large area pattern, a punching line of the large area pattern, and an imaginary line connecting the peripheral line and the punching line.
Namely, the large area pattern can not be recognized as diagram information but as only the connecting elements of the peripheral line, the punching line, and the imaginary line connecting the peripheral line and the punching line.
As a result, it becomes possible to treat the large area pattern in the unified form as lines included in the above-mentioned connecting elements and to recognize the physical connection of the connecting elements including the large area pattern at a high speed.
Also, in the present invention according to claim 9, a land directly connected to the large area pattern or included in the large area pattern may be regarded as being directly or indirectly connected to the peripheral line, the punching line, the imaginary line, or a land directly connected to one of these lines with a second imaginary line.
Namely, if the large area pattern is regarded as being the peripheral line, the punching line, and the imaginary line, where these lines will be hereinafter occasionally referred to as a large area connecting pattern, there is a possibility that the land, where this land will be hereinafter occasionally referred to as an inner land of the large area pattern, directly connected to the large area pattern or included in the same assumes the state in which it is not physically connected to the large area connecting pattern.
Thus, the inner land of the large area pattern can be directly connected to the large area connecting pattern with the imaginary line or can be indirectly connected to the large area connecting pattern by connecting the inner lands directly connected with the imaginary line.
As a result, it becomes possible to recognize the physical connection of the connecting elements including the inner land at a high speed.
Also, in the present invention according to claim 10, a cutting of the large area pattern may be recognized by cutting at least one of the peripheral line and the punching line and by adding a second imaginary line.
Namely, when the large area pattern is recognized and cut as the diagram information, it takes time to process the operation. Therefore, the large area pattern cut can be regarded as being composed of the cutting line of at least one of the peripheral line, the punching line, and the imaginary line as well as the second imaginary line added.
As a result, it becomes possible to recognize the physical connection of the connecting elements including the large area pattern cut at a high speed.
Also, in the present invention according to claim 11, a separation of a land directly connected to the large area pattern or included in the large area pattern from the large area pattern may be recognized by cutting at least one of the peripheral line, the punching line, and the second imaginary line.
Namely, the large area pattern and the land directly connected to the large area pattern or included in the same are firstly regarded as the large area connecting pattern. The land can be separated from the large area pattern by cutting the line connected to the land.
As a result, it becomes possible to recognize the separation of the land directly connected to the large area pattern or included in the same at a high speed.
Also, in the present invention according to claim 12, a cutting of the land may be recognized by cutting a peripheral line of the land and by adding an imaginary line.
Namely, in the same way as the large area pattern, the cutting of the land requires the recognition of the land as the diagram information. Accordingly, it takes time to process the operation.
The cut land is regarded as being composed of the peripheral line whose land is cut and the added imaginary line.
As a result, it becomes possible to recognize the physical connection of the connecting elements including the cut land at a high speed.
Also, in the present invention according to claim 13, a line cut by a circuit modification may be provided with a priority order of a cutting.
Namely, when the connecting elements including the large area pattern processed as the diagram information is physically cut, the priority order of the cutting position can not be considered since the recognition of the large area pattern has a priority.
Therefore, the large area pattern is regarded as a large area connecting pattern (aggregation of lines). As a result, it becomes possible to decide the priority order of the cutting of the lines including the large area connecting pattern and to designate an adequate cutting line.
Also, in the present invention according to claim 14, the net may include the attribute of a signal pattern of an MST wiring, a single stroke drawing-wiring, or a single stroke drawing-wiring for designating a connection order, or of a large area connecting pattern including a loop pattern, and when the attribute is the large area connecting pattern the connection order of the connecting elements may be determined by using a connecting element-unique decision method.
Namely, the net is classified into one of the signal patterns of the MST wiring, the single stroke drawing-wiring or a single stroke drawing-wiring for designating the connection order, and of the large area connecting pattern including the loop pattern. When the net is the large area connecting pattern, the connection order of the net is determined by the connecting element-unique decision method to set the KP addresses and the NKP addresses.
As a result, it becomes possible to recognize the physical connection of the large area connecting pattern including the loop pattern at a high speed.